The objectives of this research are (a) to develop a model for predicting the speed of VLSI (very large scale integrated) algorithms; (b) to study the feasibility of a new design technique for finding global, time-optimized VLSI architectures for a class of time-critical arithmetic computations; (c) to investigate and formulate explicitly design tradeoffs among throughput, latency and chip area; (d) to develop and automate new procedures for designing optimal VLSI architectures; and (e) to evaluate the benefits of the proposed design technique.
