This research is to develop test procedures for robust testing and design for testability (DFT) of CMOS circuits. The most likely faults in CMOS circuits are stuck-open, stuck-at and bridging faults. Thus the traditional stuck-at fault model is inadequate for MOS Technologies. Furthermore, a test set for a CMOS circuit may be invalidated by arbitrary delay signals and charge distribution among the internal nodes of the CMOS gates in the circuit. Professor Jha is developing methods to generate test sets to robustly test for faults in spite of delays and charge distribution. His approach is based on two- pattern tests to detect faults from a comprehensive fault model via logic and current monitoring. This avoids an increase in test generation time in order to gain comprehensive fault coverage. The DFT research is based on a theoretical result of Professor Jha that a universal test set can be found which is valid for all implementations from a class of CMOS circuits. Finally, testing issues related to dynamic CMOS circuits are being investigated because they enjoy the advantage of greater testability over fully complementary CMOS circuits.
