Professor Muroga's research is on VLSI design synthesis and starts with the use of the negative or NOR gate as the basic logic gate for IC design. He has developed design tools to automatically solve various IC design problems and integrated them into a synthesis system, SYLON. His research is on improving SYLON's capability to design compact networks with a large number of inputs. He is also modifying SYLON to design networks which are fast on critical paths. Compaction of ROMs is being addressed using a novel technique of storing a disjunction of minterms at each crosspoint of memory lines, instead of single minterm. When the minterm density is either high or low, or when the number of minterms is small, there is good compaction. Synthesized designs are expected to be competitive with manual designs. The proposed research is in an important area of automated design of VLSI chips, called design synthesis. The Principal Investigator's approach is novel. He is internationally recognized as an expert researcher in this area, has a history of quality research, and the potential to continue producing good research.
