Research is on physical design and synthesis of IC's, and on reliable IC designs. Theory of VLSI design model and methodologies is being used to understand layout problems for complex IC designs. Research problems being addressed include: multi-layer routing, pin assignment, placement of flexible modules, module orientation, and placement of standard cells. Two approaches to reliable designs are being investigated. The first is to identify minimal sets of redundant elements that are needed to replace defective elements in both homogeneous and non-homogeneous arrays. The minimal sets are called minimum covering sets. Second is an effort to develop a general model for fault coverage problems in reconfigurable chips. The model is capable of capturing a large class of possible relationships between redundant elements and defective elements.
