This research addresses the problem of VLSI circuit layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. Design problems here are computationally intractable. The P.I. is studying both computational and algorithmic aspects of solution methods, and devising tools that can harness the enormous complexity of the design problems. Research topics are: (1) development of fast algorithms for floorplan designs with rectilinear modules; (2) channel routing techniques for designs with rectilinear cells; (3) via minimization methods based on criteria of manufacturing cost and complexity, and circuit performance and reliability; (4) new algorithms for multi-layer topological channel routing; (5) automation of leaf cell generation; and (6) new approaches to parallel simulated annealing applicable to solving these design problems. This research investigates the problem of automating IC layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. The P.I. has novel ideas, which show promise in solving the automation problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.
