Analog interface circuitry often limits the performance of DSP based signal processing systems. Since analog circuitry will not shrink as much as digital circuitry with device scaling due to performance, matching, and noise considerations; schemes for digitally correcting or adjusting for analog circuit errors are very attractive in submicron IC technologies. In this work, techniques to improve MOS analog interface circuitry are being investigated. Parallel switched-capacitor filter architectures, which will achieve an increase in sampling rate with an increase in silicon real estate, are considered. Additionally, digital techniques for realizing small shifts in the frequency response of switched-capacitor filters are researched. Oversampled delta-sigma modulation data converters are investigated. The goal is to achieve increased sampling rates and improved performance using new switching schemes. And since shrinking device dimensions for a reduction in the power supply voltage, analog circuits operating off a 3-Volt supply are also explored. The proposed architectures are evaluated using specially written computer programs and available circuit simulators. Extensive simulation of the most promising architectures and design and layout of experimental test circuits are carried out. Suitable circuits are fabricated using MOSIS facility.
