This is an investigation of high level language specifications for IC design using the language, "SBL" as a vehicle. The focus of the research is on development of SBL design tools and experimentation with them. In particular, research is being carried out on: coupling present SBL compilers and simulators to lower level tools - the controller generator, PLA generator, and SLS simulator. The simplification of the SBL syntax is being pursued by removal of recursion, FOR and VECTOR constructs from the behavioral specification in favor of manipulations of finite sets. Also, concepts for a graphical front end to simplify the use of the language for practicing designers are being explored.
