This research concerns applying the linear RC modeling technique to model empirically timing delays in CMOS circuits. A tool, which automatically characterizes effective resistances and capacitances of MOSFETSs, is being designed for use in switch level timing simulators or analyzers based on linear RC delay models. Focus is on assessment and improvement of accuracy limitations in the model, namely: linear resistance approximation of the nonlinear MOSFET characteristic; single time constant approximation of the multiple pole network function; and step input waveform approximation. Techniques include: exploiting nonlinear body effect in the transmission gate to improve linear resistance approximation; using a simple single time constant model with an option for using a more accurate two time constant model; and using a piecewise linear characterization of the input rise/fall time effect.
