This project studies various configurations of shared busses in a Multistage Interconnection Network (MIN) based system in order to maintain cache coherence. These busses can be put separately or inside the MIN switches. It is also possible to avoid using shared busses by redesigning a MIN switch to handle broadcasting. The design and analysis of these cache coherence protocols are the research objectives of this project. A thorough analysis and comparison of various approaches can guide the future multiprocessor system designers in their design process. Multiprocessor organizations are generally defined based on their processor memory interconnections. MINs form a very suitable interconnection medium for building large scale multiprocessor systems. The efficiency of these systems can be further enhanced by putting cache memories with the processors to reduce the memory access demands. However, such cache memories give rise to inconsistency of shared data due to lack of coordination among the processors while changing their shared cache contents. A hardware solution to this problem is to broadcast the state changes through a shared bus interconnection. Since MINs do not have a shared bus, maintaining cache coherence in MIN based multiprocessors poses a serious challenge for research.
