This research is to: (a) study the problem of current surges in GaAs and ECL circuits to better understand their impacts on chip reliability, (b) develop automated techniques to analyze power, ground and clock distribution systems in order to detect potential reliability problems, (c) find design rules required for enduring reliability, and (d) incorporate design rules and guidelines into tools for design of high performance circuits. Transmission line models for interconnects in IC's are being explored. Analysis methods based on numerical techniques coupled with transmission line theory are being developed. Optimization techniques are being devised for solving problems of effective utilization of chip area. The study of current surges is being approached using experimental, stochastic and analytic techniques.
