This research is on performance driven partitioning for high speed and high density circuit design. Tools for an automatic partitioning system which divides circuits from the system level to basic layout modules are being developed. For systems of several million gates, a technique, called the ratio cut, is used to define the hierarchy of the system. The ratio cut is used to identify the cluster structure and thus organize the system into a tree structure. A heuristic ratio cut algorithm is being explored for use in hierarchal partitioning of the design. Once a partition has been made there is an optimization problem. Solutions to this problem are being investigated using neural nets, partitioning on special graphs and other methods.
