Computer architectures dominated by control logic are an important class since many applications specific designs are dominated by design of the control logic. This research is developing new optimization algorithms for behavioral synthesis of control dominated machines. Research is being done on: a. how to partition the behavioral synthesis process into manageable compilation steps, b. finding optimization algorithms to implement the compilation steps, c. determining how various optimizations interact, and d. developing reliable methods to estimate hardware costs to drive optimization. An experimental behavioral synthesis compiler is being built and will be used to experiment with real examples to test the optimization algorithms.
