This research is on developing a new fault tolerant design method, based on the self-checking checker designs. The focus is on combinational and sequential circuits based on self-check concepts and exploitation of self-checking systems for testability. A design methodology based on theoretical results for the design of self-checking circuits is being investigated. Efficient codes, which can be used to encode the outputs of functional circuits such that the overhead is low, are being used in the research. The work is oriented primarily to CMOS technology.
