This research is using the combinatorial optimization capabilities of neural networks to devise algorithms for solving repair problems in IC chips. Two classes of array repair problems are being examined. The first is repair by replacement of rows and columns (as in memory arrays). The second is repair by replacement of individual cells (as in systolic arrays and iterative logic). Theoretical models of array repair problems are being analyzed and simulated to measure the performance of neural repair algorithms. Electronic neural networks that will execute the neural repair algorithms for memory, systolic and iterative arrays are being designed and fabricated.
