This research involves exploring a background electronic trimming principle to compensate for errors arising from the component mismatch and the process variations in data converters and filters and to prove its effectiveness through theoretical simulations and experimental prototyping. The basic idea behind this work is to replace the component trimming procedure usually done in the factory prior to chip packaging by a hidden electronic calibration running in the background. The goal is to improve the performance of inherently fast data conversion and filtering systems by maintaining simple system architectures and moving the operation of sophisticated trimming circuits to the background. As a result, systems of this kind can be faster than systems electronically calibrated in foreground. This basic research will help to develop a family of high-performance monolithic analog/digital interface circuits with premium speeds not readily available in monolithic forms.
