The gap between huge data requirements of many applications and limited capabilities of transmission and storage systems dictated the need for developing high-performance data compression hardware. This research focuses on the study and implementation of nonstationary multi-alphabet source coding algorithms suitable for VLSI implementations, given the current and near-future technology; the implementation of high-throughput circuits for real-time applications; and the determination of an optimal tradeoff between the compression performance and circuit configurations given constrained chip area. The developed algorithms and circuits are excepted to offer more cost-effective data compression for communication and storage systems.
