Dai Interconnection topology and metrics needed for laying out high-speed interconnections in multi-chip modules are being pursued. The first topic is optimal design of transmission lines for multi-chip modules (MCM). These are self-damped lossy transmission lines in a tree network, which propagates high-speed signals. Algorithms to implement a robust method for designing these transmission lines are being developed. Attention is paid to distortion-free signal propagation, cross-talk, switching noise, and thermal resistance. The second topic is routing of clock signals for optimum system performance. An algorithm is being developed to construct a planer clock tree which can be embedded on a single layer of metal. Path length from the clock source to each clock terminal is exactly the same. The third topic is a multiple bus network for parallel processing which matches the MCM requirements of higher I/O pin count and inter- chip routing density. An algorithm with good fault tolerant properties that leads to uniform bus load and processor fanout is being developed.
