In this proposal, number-theoretic techniques are considered to provide hardware modularity that facilitates high data rates, testability, reliability and fault tolerance in VLSI design. A research program is proposed that will address questions of reliability and fault tolerance on both the integrated circuit and the higher system level. Modular designs of a convolutional back-projection (CBP) digital processor for synthetic aperture radar (SAR) image processing will be studied as vehicles to address both circuit and system level fault tolerance, and to study the interaction between circuit level error checking and system level fault tolerance mechanisms.
