This research studies the role and the performance of multi-level caches in scalable shared memory multiprocessors. The objectives of this project are: (1) evaluate and characterize performance of multi-level caches for multiprocessors as a function of cache parameters, cache coherency protocol, and program characteristics using trace-driven simulations; (2) evaluate cost-performance tradeoffs in selecting various multi-level cache configurations for scalable shared memory architectures using different workload parameters; (3) investigate and develop trace reduction and sampling techniques to speed up simulations to study multi-level cache performance in multiprocessors;(4) develop analytical models to evaluate performance of multi-level caches in scalable architectures; and (5) investigate what minimal set of characteristic metrics must be measured to predict multi-level cache performance over a wide range of cache parameters.
