Pillage The research is on developing simulation capabilities at the system level, which are as powerful as those at the chip level. To this end, tools which are applicable at the integrated circuit, packaging, module, and board levels without loss of generality are being developed. Specific areas being investigated are: fast extraction techniques which trade off some accuracy for efficiency; and simulation models and techniques to enable topdown design. Timing analysis of boards or multi-chip modules requires development of tools for the extraction, characterization and simulation of transmission lines at the system simulation level. Toward this end interconnect macro- models, similar to those for on-chip RC interconnect circuits, which are compatible with system-level design automation tools, are being explored.
