The purpose of this proposal is to study the numerical properties of a new adaptive filter algorithm recently introduced by the PI - the Fast Exact Least Mean Square (FELMS) - with a view towards VLSI implementation. At least one custom/semi-custom digital signal processor chip will be designed to implement the FELMS adaptive algorithm and/or related algorithms. A new high-level design automation tool, Olympus (developed at Stanford University), will be employed in the chip design. This approach will reduce the design time and give a quick turn-around. It will also serve to exercise these hitherto untested synthesis tools for applications such as the above. This research will be inter-disciplinary, combining VLSI CAD and Application Specific Integrated Circuit (ASIC)-based architectures, to implement new algorithms and structures for adaptive filters.
