This research investigates instruction-level parallel (ILP) processors. The goal is to develop processors that can sustain over 10 instructions per cycle when executing arbitrary non-numeric applications such as compilers, simulators, CAD, text processing, and database programs. The research builds on the previous studies of ILP to expand the foundation for ILP processors. A novel paradigm for ILP processors, the multiscalar processing paradigm, continues to be developed, with the goal of bringing the multiscalar paradigm into the mainstream of processor design. Issues relevant to the operation of a multiscalar processor such as data memory systems, instruction memory systems, inter-operation communication mechanisms, and task specification and execution, are studied using detailed simulation models. Also investigated is software support for multiscalar processors.
