Adding instruction-level parallelism to an architecture is a technique becoming popular for increasing power in modern computers. One consequence of this trend is the need to include instruction scheduling in a compiler. ``Global Instruction Scheduling Without Copies'' investigates a method of global sch-eduling which, unlike other global scheduling techniques does not suffer from the need for compensation copies. The work's goal is refining a technique for scheduling which will work better than existing methods for ILP architectures with limited parallelism, a characteristic of ILP architectures found today, and expected for superscalar architectures in the future. The study investigates dominator-path scheduling (DPS) in some detail and compare DPS to other global scheduling methods. Since DPS is better suited than other scheduling techniques for the levels of ILP found in current architectures, one outcome of the research is the ability to generate better code for currently popular computers. Additionally, the work quantifies the parallelism available in imperative programs when compensation copies are not allowed. This measurement of such parallelism will influence the design of ILP architectures in the future.
