Orailoglu This research is on automatic synthesis of fault-tolerant micro-architectures. Two areas are being investigated. One is an exploration of methodologies and CAD tools for synthesis of self-recovering micro-architectures. The model for self- recovering designs is a flow-graph representation in which partial results from two copies of the graph are periodically compared at a checkpoint. Research is on scheduling, allocation, binding, and checkpoint insertion. The second is an investigation of techniques automatic synthesis of fault-secure micro-architectures. Salient features of the research are: algorithms for region delineation so as to ameliorate hardware bottlenecks, and region scheduling so as to relax and weaken precedence constraints between regions.
