The goal of this research is to develop an innovative and unified methodology for designing self-repairable ultra-large integated (ULSI) circuits and multi-chip module (MCM) chips. This research will exploit the combinatorial optimization capabilities offered by adaptive circuits consisting of simple threshold devices interconnected programmable resistive networks for the purpose of adding a self-repair capability to hardware devices. The proposed research will be conducted in three phases. In the first phase, theoretical models for both regular array logic and unstructured random logic repar problems will be developed, and entensive simulations will be performed to measure the performance of the adaptive self-repair circuits. In the second phase, adaptive circuits will be designed using CMOS technology, and experimental chips willbe fabricated and tested as "proofs. of concept." In the third phase, software will be developed to allow the proposed adaptive bult-in-self-repar circuits to be automatically synthesized by VLSI/CAD software and invorporated within macro blocks. This project initiates a new area of research that is a natural sequel to the on-going works in the fields of Built-In- Self-Testing (BIST) and Design for Testability (DFT).
