This project is an investigation into a new generation of hierarchical partitioning methods motivated by the need to 1) cope with high circuit complexity, 2) improve a system's performance under I/O pin count constraints, and 3) control intermodule delay in order to optimize system performance. The principal investigator proposes to extend previous partitioning research by adopting different circuit models including petri nets, data flows, and state machines, by improving the efficiency and effectiveness of the methods, and by deriving theoretical results on variations of partitioning formulations. He plans to apply partitioning methods to netlist mappings for various hardware emulation machines and to find potential applications of these methods to VLSI design problems
