The proposed research deals with analytically verifying the satisfaction of timing constraints of component interfaces in board level circuits. A methodology, VITCh (VLSI Interface Timing Checker), that will allow the analytic timing verification of realistic board-level circuits through new models of behavior and verification is proposed. A hierarchial model of interface behavior that allows the task to be decomposed to minimize overall complexity is also proposed. The proposed model will allow efficient timing analysis of board-level circuits and thereby enable the analytical verification of large and complex circuits that existing approaches are unable to verify. A CAD system implementing VITCh to provide a testbed for experimentally validating the model and methodology is proposed as part of the project. The proposer attempts to solve the timing analysis problem by decomposing the task into several subtasks that can be executed concurrently. Each subtask is performed such that timing constraints are verified during the process of circuit behavior enumeration and eliminates the need to build and analyze composite representations of circuit behavior. The research plan includes testing VITCh on circuits ranging from tens to hundreds of components to establish the range of applicability of the algorithm as a function of circuit size.
