This research explores a new delay test set, called a delay- verification test set, which detects the presence of any path delay faults that can affect the timing of the circuit. The approach is to find necessary and sufficient conditions for delay verifiability; i.e., the existence of a complete delay-verification test set. Algorithms for the synthesis of area-efficient, delay- verifiable circuits and the generation of delay verification test sets are being developed. A second topic being explored is a design and test methodology for sequential circuits without scan latches in functional paths. A method, based on clock suppression, is being used to generate transitions on state variables for delay testing. State assignment techniques to improve delay-fault testability without scan and clock suppression are being investigated.
