This project will investigate a coherent cache parallel computer in chich decisions on a particular cache block are based upon the run time history of the particualr instruction accessing the block will be undertaken. The cache management scheme will detect and exploit a variety of insturction behaviors. The system could have certain sinstructions invalidate after reading, force a cache block to be copied to another processor, or, on a miss, bring in a cache block with a predetermined invalidation time. These will result in fewer messages and lower latency. In the proposed reserch each of these techniques will be developed in detail and evaluated using execution driven simulations. The results will establish the efficacy of the technique which can be used to improve the performance of a wide range of aprallel computers from office fileservers to supercomputers.
