Realistic formulations of performance-driven layout are the focus of this research. Accurate models of circuit delay are being sought. These models include technology parameters, such as capacitance, resistance, inductance, etc. The approach is to study delay-optimal trees to define an envelope of achievable routing performance. Methods for constructing near-optimal layouts are being investigated. Additionally, the routing problem is being recast as one of constructing low-delay routing graphs where cycles are allowed. This can have the advantage of designs being tolerant to certain types of open faults due to manufacturing defects or electro-migration.
