This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independent models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the state of the art and to identify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniques will include gate design level approaches, but will focus primarily on organizational and instruction set architectural approaches that inherently have a lower power requirement. The end goals of this research s to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two ways that can broadly impact the continuing evolution of VLSI Technology and its successful use in computing.
