This grant will support the American participants in a workshop on Applied Formal Methods to be held in Hyderabad, India, in December 1996. The goal of the workshop is to bring together several international experts from the U.S., India, and elsewhere with the purpose of capturing the state of the art in the technology and the state of practice in the applications of formal methods. The workshop scope includes the study of specification languages and logics and verification methods, such as theorem proving, model checking, and safety analysis. Formal methods are increasingly applied to the core algorithms in safety-critical systems and in the verification of hardware circuit designs. A workshop of this nature provides a timely means for developing a common understanding of the capabilities and the potential applications of these technologies. The organizers will edit a technical report providing an up-to-date survey of applied formal methods. ***
