The research portion of this project advances the study of simultaneous multithreading, a processor architecture technique aimed at increasing the utilization of the execution resources in processors that issue multiple instructions in each clock cycle. The research objectives are threefold: (1) to re-evaluate memory system architecture in light of a simultaneous multithreaded workload; (2) to investigate processor issues such as synchronization methods and strategies to deal with large register files; (3) to address the implications of simultaneous multithreading on the software system. The work entails revamping of an existing simulator for multithreaded processors, and use of the new simulator in evaluating alternatives. The educational portion concentrates on a revamping of the department curriculum in computer architecture. New graduate courses on computer architecture are being introduced, and simultaneous multithreading is being integrated into the core architecture courses for undergraduates. All course work is being enhanced with hands-on experimentation with instruction-level simulation.
