This research is on asynchronous (self-timed) VLSI circuits. High performance design, and testing of self-timed circuits are being investigated. Research focuses on developing tools and methodologies in the following areas. First, a new data transmission scheme for self-timed VLSI systems, the bounded-skew protocol, is being defined. Second, techniques and tools to test self-timed circuits with special emphasis on modeling and testing the actual delays in asynchronous circuits are being developed. Third, methods to reduce power consumption in self-timed circuits by trading concurrency for power and using voltage scaling techniques are being examined. Finally, the potential of asynchronous VLSI design is being demonstrated through implementing prototype VLSI chips in arithmetic and signal processing applications.
