This research involves the creation of a co-processor architecture evaluation environment which integrates architecture-level simulation with industrial CAD tools. The end-goal is to facilitate the design of high-performance domain-specific co-processors. In the evaluation environment, the designer will have the capability of 'test driving' a wide variety of design alternatives with respect to real application ppograms. The mechanism is to `drop-in' components into predetermined templates, gauge their effect on virtual machine instruction execution, and use that information to evaluate virtual machine instruction traces. There are three aspects to this research: (i) integrating existing or user-constructed component libraries and synthesis tools into an architecture- level model generator, (ii) integrating the same into an interprocessor network simulator, and (iii) extending an existing architecture-level simulator to include data parallel SPMD architectures. A graphic user interface is being developed to help the user mix-and-match components. The resulting environment will target not only professional designers, but also students in computer and advanced digital design classes.
