Roundoff error and catastrophic cancellation in floating point computations can quickly lead to inaccurate results. The research objectives of this project are to design, develop, and evaluate hardware support for avoiding such errors. The project will concentrate on hardware and instruction set modifications to support variable-precision arithmetic and interval arithmetic. Work will include the development of algorithms, design and simulation of hardware support, and evaluation of cost, performance, and power consumption of the resulting hardware. Promising designs will be fabricated. Education in computer architecture and processor design is being addressed by the development of courses, by encouragement of undergraduate and graduate research, and by outreach to middle school and high school students.
