This research is on test methods for finding process parameter faults in memories embedded in advanced technology chips. The effect of threshold voltage variation and noise (e.g., leakage, charge sharing, crosstalk, etc.) on the functionality of a memory cell is modeled (using circuit simulation and analysis) in terms of read/write error margins and variance of access delays. Algorithms for failure modes in memories, based on fault models generated from process and circuit studies, are being developed. Tools based on them allow functional and parametric testing of static RAMs. The issues of testing gigabit stretchable DRAMs with multi-valued address decoding schemes are being analyzed from an algorithmic standpoint. Fault models, pertaining to these analog-like components, and memory testing algorithms are being explored. One methodology for testing high-density SRAMs and multivalued stretchable DRAMs with mixed-mode circuits, uses the measure of the harmonic distortion of a pure sinusoidal input signal in order to extract detection and diagnosis information for various technology, parametric and layout-related faults in the memory chip.
