This research is on design of low-power hardware for digital signal processing (DSP) and communications applications. The approach incorporates both high-level (algorithmic) and low-level (circuit) parameters, and includes novel methods for design exploration, power estimation and low-power circuit synthesis. Key features of the approach include: a.) joint optimization of algorithmic performance with power dissipation, b.) integration of high-level algorithmic and low-level circuit issues via high-level power estimation, and c.) explicit incorporation of signal statistics at all levels of design.
