Compilation technology has contributed to the success of computational science by allowing users to achieve high program performance without worrying excessively about details of the underlying hardware architecture. Most compiler optimizations focus on improving computation efficiency, but the growing disparity between processor and memory speeds has made exploiting reuse of registers and cache important as well. This project will explore techniques for improving program performance by modifying the data layout in a program to improving spatial locality and avoid adverse memory effects such as conflict misses and false sharing. Target optimizations include modifying the base addresses of variables, changing fields offsets within structures, group-and-transpose of related data, padding, transposing, and reindexing array dimensions. The main goal of this project is to develop heuristics for guiding data layout optimizations, both individually and as part of an overall optimization strategy which includes computation transformations. To evaluate the impact on scientific applications, optimizations will be implemented as passes in the Stanford SUIF compiler and tested on benchmark suites such as Perfect, NAS, and SPEC for both scalar and parallel architectures.
