This research is on developing algorithms and tools to synthesize testable digital sequential circuits. The testable synthesis problem has in the past been dealt with as two independent problems namely, the state assignment problem and the testing problem. Algorithms and tools that can synthesize area-efficient and testable designs of sequential circuits represented as finite state machines are being developed. Methods of partitioning and re-synthesizing large sequential circuits using the CAD tools and/or the test architectures developed in this project and generation of test vectors for the resulting circuits are being explored.