We propose a new paradigm for system design in which the algorithm and circuit implementations are jointly designed to achieve high-performance while minimizing average power consumption. We propose to drive the research using a case study of an adaptive equalizer/decoder where both algorithm selection and asynchronous hardware design will be tackled using a Minimum Average Complexity (MAC) approach. In particular, we will develop a detailed asynchronous design of representative components of a MAC optimized mobile radio receiver, variable complexity algorithms for joint adaptive equalization and decoding, a characterization of the average computational load of these algorithms for a typical mobile user, general procedures for MAC algorithm optimization, an architecture for the new algorithms and a quantitative estimate of the power savings relative to a standard design.
