With the anticipated ability to build chips containing one billion transistors, a larger amount of memory and functionality may be available on a single chip. One challenge is how to manage and configure all these resources for optimal performance and power dissipation. This research explores the problem of determining optimal use of all available resources on chip on an application by application basis. Where reconfigurable logic is available for use (either on chip or off) synthesis tools can be used to determine optimal hardware/software partitioning of the application as well as to architecturally synthesize the hardware portions onto reconfigurable logic. Tools are being developed to produce high-performance power-conscious designs. Various applications are being explored to determine the effectiveness of these tools. The applications are being run on reconfigurable computing platforms designed at Brown's computer engineering laboratory. The topics of low-power and high-performance computer design, and advanced computer architecture design are being introduced to the curriculum via new courses and the modification of existing ones. Approaches to advising and mentoring students at levels from pre-college to graduate are being developed. Emphasis is in mentoring and outreach services to young women just entering a career in science or engineering.
