Cores containing intellectual property (IP) are being used widely for cost-effective and timely design of systems-on chip (SOC). This presents a problem for manufacturing test in that cores contain proprietary information, and effective test methods are difficult to develop. This research is developing a new Query/Request (Q/R) paradigm to enable development of tests for a SOC without obtaining direct access to the core vendors' IP. New procedures for simulation, fault simulation, test generation are being explored. These procedures encapsulate information about each core, and provide only certain types of information that do not contain IP in response to a Q/R from the system level module. A system level module to develop tests for the entire SOC is also being developed. Tools being developed under the Q/R paradigm research include fault simulators, test generators, procedures for design-for-testability (DFT), and built-in self-test (BIST) circuitry.
