This project is investigating computer architectures based on a distributed, decentralized (DD) approach to computing. It is now necessary to re-examine traditional concepts of processor architecture because the gap between processor cycle time and relative memory access time is increasing, distributing a high-speed synchronous clock to billions of transistors is difficult, and as processors become more complex and compiler analysis becomes more intelligent, their interface must be improved. In this research, the underlying processor model used is both distributed and decentralized in resource allocation, consisting of multiple independently programmable processing elements, elasticity connected to one another and to memory via FIFO queues. This approach is capable of tolerating memory latency, overcoming the clock distribution problem, and facilitating the transfer of compiler information to the hardware. This project includes the development of compiler technology and a hierarchical simulation framework to demonstrate these claims.
