This proposal investigates a new class of processors and their associated compilers, Tiger processors, which TIghtly couple a GEneral-purpose processor with a Reconfigurable function unit (RFU). The RFU can be configured, at run-time, to implement a function as a hardware circuit. Tiger processors offer the flexibility of a general-purpose microprocessor with the performance of a custom circuit.
Tiger processors offer high performance and efficiency because they contain an RFU, which, when needed, can be configured to implement hardware matched to any individual application. Tiger processors can realize an application's parallelism on all levels: MIMD, SIMD, instruction-level, pipeline, and bit-level.
The two requirements to realizing the potential of these processors, investigated in this proposal, are (1) developing robust compilers which quickly produce efficient executables from any high-level programming language, and (2) investigating the proper interface between the RFU and the general-purpose processor.
The objective of this research is to allow programs to obtain performance approaching that of custom hardware from a general-purpose device. Tiger processors will both increase performance and reduce the cost of systems because there will be no need to augment systems with custom hardware and its associated design overhead.
