As CMOS technology advances into the 80 nanometer generation and beyond, the manufacturing process is having an increasingly constraining effect on physical layout design and verification. To maximize yield, process engineers must achieve predictability and uniformity of manufactured device and interconnect attributes. This project investigates newly critical issues in the interface between layout design and manufacturability, such as layout modification for reduced variability of chemical-mechanical polishing, design which is amenable to optical lithography using phase-shifting masks and optical proximity correction, and other problems. This project is developing robust testbeds, algorithms and tools to address these important problems, and is interacting with industry partners to tailor the proposed approaches to address real objectives on actual test cases and production runs.
