This research is concerned with statistically based computer-aided design and manufacturing of VLSI processes and circuits. Due to the complexity of VLSI circuits, the design cycle must contain a design verification feedback loop. In a fully automated design system (e.g., silicon compilers), several verification tools (e.g. design rule checking, logic simulation) may be unnecessary because the system produces correct designs. However, there exists a need for IC performance evaluation prior to IC manufacturing. Circuit simulation is the most powerful and widely used technique for performance verification. The accuracy of such a verification depends strongly on the accuracy of the device model parameters used in the simulation. These model parameters can be determined by a process simulator which contains physical models of the IC fabrication process steps and semiconductor devices. The objective of the research is to develop efficient techniques for process/device simulation and apply them to a number of design tasks such as nominal design, worst-case design and statistical design.
