The primary objective of the research is to develop reliable methods to predict residual (fabrication) stress and applied thermal stress levels in microelectronic device structures. In addition, the research will also suggest ways to systematically reduce stresses arising during fabrication. The types of structures for which this research will be applicable are: semiconductor wafers, integrated circuit chips, hybrid circuits, and heterojunction lasers. Stresses induced during forming can adversely effect reliability of the end product and cause premature failure of devices via fracture, anomalous diffusion of dopants, or deleterious electromigration. Furthermore, high stresses also occur during subsequent operation due to substantial temperature gradients within components. Both fabrication and operating stresses arise because of the wide disparity of thermal expansion between various device materials, such as silicon and various thin film oxides or metals. Current methods for predicting such stresses are very approximate. The research will use a variety of solid mechanics principles to address some unsolved problems regarding layered electronic structures, particularly interfacial stresses in wafers. Simple but useful stress analysis formulas will be developed to assist preliminary mechanical design of electronic devices, while finite element stress analysis will be employed to study the detailed nature of complex singular stress systems which must exist at material interfaces.
