9400051 Kuo This grant provides support for research on microelectronic circuit design for reliability by means of system burn-in, which can remove many of the residual defects remaining after component and subsystem burn-in. Burn-in techniques are widely applied to integrated circuits (ICs) to enhance reliability. However, complex system configurations often make it difficult to formulate optimal burn-in strategies. This research will address the use of a non-parametric design approach and the generalized Dirichlet process to determine system burn-time. In addition, it will consider the impact of incompatibility that reduces system reliability and that affects the optimal burn-in strategy for both component and subsystem burn-in. If successful, this research will provide an approach, at the design stage, for system designers to (1) determine the optimal burn-in strategy for new ICs, (2) find the optimal burn-in times at the component, subsystem, and system levels, (3) implement the optimal burn-in strategy by using the field failure data available from IC manufacturers, and (4) better understand the failure mechanisms of new ICs, enabling improvement of their reliability and quality in the manufacturing process. These advances could help to improve competitiveness of the United States IC industry.
