Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically reduce the power consumption while growing in size, flexibility and usefulness. The goal of this project is to develop the first mapping algorithm for floating-gate-based large-scale FPAAs. The target FPAA device consists of floating-gate transistors, which are standard pFET devices whose gate terminals are not connected to signals except through capacitors. Because the gate terminal is well insulated from external signals, the floating gate can maintain a permanent charge. The computational logic in the FPAA is organized in a compact computational analog block (CAB) that consists of op-amps, transistors, multiplier, programmable capacitors, and filters. CABs are tiled across the chip in a regular mesh-type architecture with busses and local interconnects between them. The major parasitic effects on FPAA chips are due to parasitic resistance and capacitance on FPAA interconnects. Therefore, the primary objective during mapping is to minimize the total number of wireless and switches involved in each interconnect. The mapping process is divided into three: CAP clustering, CAP placement, and FPAA routing. The CAB clustering algorithm tries to group analog components in the given circuit into CAB clusters under the device and wire constraints. During CAP placement, each CAB cluster is assigned to a unique CAB slot in the given FPAA architecture so that the wirelength, congestion, and performance degradation are minimized simultaneously. The FPAA router initially routes each interconnect by the shortest path while ignoring any overuse of routing resources. Then it sequentially performs ripping-up and re-routing every connection to minimize overuse of routing resources in the routing solution. The proposed mapping technology is being transferred to a startup company, and tools and training materials are made widely available through an on-line streaming video course. Graduate students involved are gaining experience in digital/analog signal processing, mixed-signal system design, and physical layout automation algorithms.
